Energy Efficient Functional Unit For A Parallel Asynchronous DSP

With the explosive growth in portable applications, power efficient computing in a Digital Signal Processor (DSP) is becoming a significant and challenging area of research. Clock-less or asynchronous timing is applied to eliminate clock generation, buffering and distribution at the system level. This paper presents the energy efficient functional unit for an asynchronous DSP implemented on four-way parallelism architecture. In particular, as is well known, arithmetic operations such as multiply or multiply-accumulate are frequently performed and are power hungry. Reducing the power dissipation in multiplier and adder without sacrificing the performance will extend the limited source of energy used in portable applications. This has led to the incorporation of an unusual parallel datapath architecture, a balanced delay tree in the multiplier, a carry-look-ahead tree adder, a novel design of Hamming distance and normalization circuit, data dependent computing and pass transistor circuits to achieve better energy efficiency. The developing flexible FU for the user and system programmer is another highlight of our works. This has led to additional cost, particularly in the implementation of the associative configuration memory. The cost can be justified by the flexibility and performance gained by user. The full-custom datapath of the FU has been implemented on 0.18m operating at 1.8 V. The preliminary results of the extracted full-custom FU layout netlist are represented which confirm that all energy efficient design techniques at the logic and circuit level demonstrate significantly improvement of the power, performance and area in functional unit.